Up to 32 × 64-bit registers, SIMD/floating-point (optional)ģ2-bit, except Thumb extension uses mixed 16- and 32-bit instructions.īi (little as default) in ARMv3 and aboveġ5 × 32-bit integer registers, including R14 (link register), but not R15 (PC, 26-bit addressing in older)ĪRM (stylised in lowercase as arm, formerly an acronym for Advanced RISC Machines and originally Acorn RISC Machine) is a family of reduced instruction set computer (RISC) instruction set architectures for computer processors, configured for various environments.

Thumb-2, Neon, Jazelle, AES, SHA, DSP, Saturated, FPv4-SP, FPv5, Heliumġ5 × 32-bit integer registers, including R14 (link register), but not R15 (PC) SVE, SVE2, SME, AES, SHA, TME All mandatory: Thumb-2, Neon, VFPv4-D16, VFPv4 obsolete: Jazelleģ2 × 128-bit registers for scalar 32- and 64-bit FP or SIMD FP or integer or cryptographyĪRMv9-R, ARMv9-M, ARMv8-R, ARMv8-M, ARMv7-A, ARMv7-R, ARMv7E-M, ARMv7-M, ARMv6-Mģ2-bit, except Thumb-2 extensions use mixed 16- and 32-bit instructions.

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